entity GATE2 is
  port (  	
	X:	in  std_logic ;
	Y:	in  std_logic ;
	F2:	out std_logic ;
	F3: out std_logic ;
  ) ;
end GATE2 ;

architecture behv of GATE2 is
begin
	F2 <= X or Y ;
	F3 <= not X ; 
end behv ;

entity GATE1 is
  port (  	
  	A:	in  std_logic ;
	B:	in  std_logic ;
	F1:	out std_logic ;
  );
end GATE1;

architecture behv of GATE1 is
begin
	F1 <= A and B;
end behv ;

entity COMB is
  port (
	input1: in  std_logic ;
	input2: in  std_logic ;
	input3: in  std_logic ;
	output: out std_logic ;
  );
end COMB;

architecture struct of COMB is
    signal wire: std_logic ;
begin
    GATE1  port map (A => input1, B => input2, F1 => wire);
    GATE2  port map (X => wire,   Y => input3, F2 => output);
end struct ;